Optimum LDPC decoder: A memory architecture problem

Erick Amador; Renaud Pacalet; Vincent Rezard

Optimum LDPC decoder: A memory architecture problem

Erick Amador
, Renaud Pacalet
, Vincent Rezard

Eurecom
Infineon Technologies France

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.

Original language	English
Title of host publication	2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Pages	891-896
Number of pages	6
Publication status	Published - 10 Nov 2009
Event	2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States Duration: 26 Jul 2009 → 31 Jul 2009

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Country/Territory	United States
City	San Francisco, CA
Period	26/07/09 → 31/07/09

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

LDPC codes
Low power architectures
Memory optimization

Cite this

@inproceedings{3e698ad652db497aa84b175165b3f814,

title = "Optimum LDPC decoder: A memory architecture problem",

abstract = "This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.",

keywords = "LDPC codes, Low power architectures, Memory optimization",

author = "Erick Amador and Renaud Pacalet and Vincent Rezard",

year = "2009",

month = nov,

day = "10",

language = "English",

isbn = "9781605584973",

series = "Proceedings - Design Automation Conference",

pages = "891--896",

booktitle = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009",

note = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009 ; Conference date: 26-07-2009 Through 31-07-2009",

}

TY - GEN

T1 - Optimum LDPC decoder

T2 - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009

AU - Amador, Erick

AU - Pacalet, Renaud

AU - Rezard, Vincent

PY - 2009/11/10

Y1 - 2009/11/10

N2 - This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.

AB - This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.

KW - LDPC codes

KW - Low power architectures

KW - Memory optimization

M3 - Conference contribution

AN - SCOPUS:70350731282

SN - 9781605584973

T3 - Proceedings - Design Automation Conference

SP - 891

EP - 896

BT - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009

Y2 - 26 July 2009 through 31 July 2009

ER -

Optimum LDPC decoder: A memory architecture problem

Abstract

Publication series

Conference

UN SDGs

Keywords

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Cite this