Parallel programming and speed up evaluation of a NoC 2-ary 4-fly

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Abstract

In this paper we make the design, the simulation and the implementation of a NoC (Network on Chip) 2-ary 4-fly in order to evaluate the speed up of an application with different NoC sizes. For the conception of the NoC, we use the tool NoCcompiler from Arteris Company. To test the performance of this NoC we integrate it as an IP (Intellectual Property) into an EDK project where masters are 16 Microblazes processors and slaves are 16 blocks memories. As an application, we choose the parallel programming to compute a filter Harris of an image 256×256. This work is implemented on Eve platform emulation called Zebu UF4. Results have proved the efficiency of this parallel architecture with a reduction equal to 90% of the execution time. The non linearity of the speed up's curve is coherent with the theorical modelisation and simulation presented in[1].

Original languageEnglish
Title of host publication2010 International Conference on Microelectronics, ICM'10
Pages156-159
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2010
Externally publishedYes
Event2010 International Conference on Microelectronics, ICM'10 - Cairo, Egypt
Duration: 19 Dec 201022 Dec 2010

Publication series

NameProceedings of the International Conference on Microelectronics, ICM

Conference

Conference2010 International Conference on Microelectronics, ICM'10
Country/TerritoryEgypt
CityCairo
Period19/12/1022/12/10

Keywords

  • 2-ary 4-fly
  • Filter Harris
  • NoC
  • NoCcompiler
  • Parallel programming
  • Speed up
  • Zebu UF4

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