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Phase Correction Algorithm for Single-Chip Wireless Motes with Crystal-Free CMOS Oscillators

  • Portland State University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Free-running oscillators allow a chip designer to minimize the size and power design requirements of a system by removing the crystal phase reference. Removing a crystal referenced phase-locked loop (PLL), introduces phase noise to the oscillator. This work demonstrates that an offline phase synchronization algorithm is able to correct the frequency variations on a free-running LC-tank based oscillator sufficient to incorporate a phase shift keying-based protocol. The data-aided implementation of the algorithm successfully demodulates and corrects the phase offset at near minimum bit error rate (BER) until Eb/N0 of 8dB after which phase noise dominates. The non-data aided mode preforms zero bit errors after Eb/N0 of 13dB, within the limits of the 8512 bits and 300 Monte Carlo iterations.

Original languageEnglish
Title of host publicationIEEE Joint Conference of the IEEE International Frequency Control Symposium and European Frequency and Time Forum, EFTF/IFCS 2025 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Edition2025
ISBN (Electronic)9798331510794
DOIs
Publication statusPublished - 1 Jan 2025
Event2025 IEEE Joint Conference of the IEEE International Frequency Control Symposium and European Frequency and Time Forum, EFTF/IFCS 2025 - Queretaro, Mexico
Duration: 12 May 202516 May 2025

Conference

Conference2025 IEEE Joint Conference of the IEEE International Frequency Control Symposium and European Frequency and Time Forum, EFTF/IFCS 2025
Country/TerritoryMexico
CityQueretaro
Period12/05/2516/05/25

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