Physical design of FPGA interconnect to prevent information leakage

Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin

doi:10.1007/978-3-540-78610-8_11

Physical design of FPGA interconnect to prevent information leakage

Sumanta Chaudhuri
, Sylvain Guilley
, Philippe Hoogvorst
, Jean Luc Danger
, Taha Beyrouthy
, Alin Razafindraibe
, Laurent Fesquet
, Marc Renaudin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

Original language	English
Title of host publication	Reconfigurable Computing
Subtitle of host publication	Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings
Pages	87-98
Number of pages	12
DOIs	https://doi.org/10.1007/978-3-540-78610-8_11
Publication status	Published - 22 Sept 2008
Event	4th International Workshop on Applied Reconfigurable Computing, ARC 2008 - London, United Kingdom Duration: 26 Mar 2008 → 28 Mar 2008

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4943 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	4th International Workshop on Applied Reconfigurable Computing, ARC 2008
Country/Territory	United Kingdom
City	London
Period	26/03/08 → 28/03/08

Access to Document

10.1007/978-3-540-78610-8_11

Cite this

Chaudhuri, S., Guilley, S., Hoogvorst, P., Danger, J. L., Beyrouthy, T., Razafindraibe, A., Fesquet, L., & Renaudin, M. (2008). Physical design of FPGA interconnect to prevent information leakage. In Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings (pp. 87-98). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4943 LNCS). https://doi.org/10.1007/978-3-540-78610-8_11

Chaudhuri, Sumanta ; Guilley, Sylvain ; Hoogvorst, Philippe et al. / Physical design of FPGA interconnect to prevent information leakage. Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. 2008. pp. 87-98 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{ff1ce4aa43ed456d89a15f696de50cac,

title = "Physical design of FPGA interconnect to prevent information leakage",

abstract = "In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn \& Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.",

author = "Sumanta Chaudhuri and Sylvain Guilley and Philippe Hoogvorst and Danger, \{Jean Luc\} and Taha Beyrouthy and Alin Razafindraibe and Laurent Fesquet and Marc Renaudin",

year = "2008",

month = sep,

day = "22",

doi = "10.1007/978-3-540-78610-8\_11",

language = "English",

isbn = "3540786090",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "87--98",

booktitle = "Reconfigurable Computing",

note = "4th International Workshop on Applied Reconfigurable Computing, ARC 2008 ; Conference date: 26-03-2008 Through 28-03-2008",

}

Chaudhuri, S, Guilley, S, Hoogvorst, P, Danger, JL, Beyrouthy, T, Razafindraibe, A, Fesquet, L & Renaudin, M 2008, Physical design of FPGA interconnect to prevent information leakage. in Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4943 LNCS, pp. 87-98, 4th International Workshop on Applied Reconfigurable Computing, ARC 2008, London, United Kingdom, 26/03/08. https://doi.org/10.1007/978-3-540-78610-8_11

Physical design of FPGA interconnect to prevent information leakage. / Chaudhuri, Sumanta; Guilley, Sylvain; Hoogvorst, Philippe et al.
Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. 2008. p. 87-98 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4943 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Physical design of FPGA interconnect to prevent information leakage

AU - Chaudhuri, Sumanta

AU - Guilley, Sylvain

AU - Hoogvorst, Philippe

AU - Danger, Jean Luc

AU - Beyrouthy, Taha

AU - Razafindraibe, Alin

AU - Fesquet, Laurent

AU - Renaudin, Marc

PY - 2008/9/22

Y1 - 2008/9/22

N2 - In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

AB - In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

U2 - 10.1007/978-3-540-78610-8_11

DO - 10.1007/978-3-540-78610-8_11

M3 - Conference contribution

AN - SCOPUS:51849153761

SN - 3540786090

SN - 9783540786092

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 87

EP - 98

BT - Reconfigurable Computing

T2 - 4th International Workshop on Applied Reconfigurable Computing, ARC 2008

Y2 - 26 March 2008 through 28 March 2008

ER -

Chaudhuri S, Guilley S, Hoogvorst P, Danger JL, Beyrouthy T, Razafindraibe A et al. Physical design of FPGA interconnect to prevent information leakage. In Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. 2008. p. 87-98. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-78610-8_11

Physical design of FPGA interconnect to prevent information leakage

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