Abstract
In this paper we propose a neuro fuzzy control of cache memories and analyzes the integration of related fuzzy and neural hardware components in the architecture of a pipelined processor. This fuzzy and neural hardware is used to support on chip cache management operations.
| Original language | English |
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| Pages | 653-658 |
| Number of pages | 6 |
| Publication status | Published - 1 Jan 1997 |
| Externally published | Yes |
| Event | Proceedings of the 1997 6th IEEE International Conference on Fussy Systems, FUZZ-IEEE'97. Part 1 (of 3) - Barcelona, Spain Duration: 1 Jul 1997 → 5 Jul 1997 |
Conference
| Conference | Proceedings of the 1997 6th IEEE International Conference on Fussy Systems, FUZZ-IEEE'97. Part 1 (of 3) |
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| City | Barcelona, Spain |
| Period | 1/07/97 → 5/07/97 |