TY - GEN
T1 - Practical metrics for evaluation of fault-tolerant logic design
AU - Stempkovskiy, Alexander
AU - Telpukhov, Dmitry
AU - Solovyev, Roman
AU - Balaka, Ekaterina
AU - Naviner, Lirida
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/4/24
Y1 - 2017/4/24
N2 - Paper presents a technology-independent metric for evaluation of logical masking properties of logic circuits and method for accurate reliability comparison of fault-tolerant logic designs. Proposed metric is based on the observability computation, providing certain trade-off between computational complexity and accuracy, reducing exponential complexity with regard to the number of elements to the linear relationship. It is based on evaluation of upper and lower bounds for the error polynomial based on the observability of gates. Simulation results of comparison with well-known observability-based method are presented for applications on the LGSynth91 and ISCAS85 benchmark circuits. It is shown that the proposed approach provides results that are more accurate on the most of the benchmark circuits while maintaining the same computational complexity. The approach for calculation of upper and lower bounds for observability-based method was generalized for multiple failures and arbitrary number of simulations. This approach has been applied to the problem of accurate reliability comparison of logic circuits, significantly reducing the number of simulations required to get an unambiguous solution.
AB - Paper presents a technology-independent metric for evaluation of logical masking properties of logic circuits and method for accurate reliability comparison of fault-tolerant logic designs. Proposed metric is based on the observability computation, providing certain trade-off between computational complexity and accuracy, reducing exponential complexity with regard to the number of elements to the linear relationship. It is based on evaluation of upper and lower bounds for the error polynomial based on the observability of gates. Simulation results of comparison with well-known observability-based method are presented for applications on the LGSynth91 and ISCAS85 benchmark circuits. It is shown that the proposed approach provides results that are more accurate on the most of the benchmark circuits while maintaining the same computational complexity. The approach for calculation of upper and lower bounds for observability-based method was generalized for multiple failures and arbitrary number of simulations. This approach has been applied to the problem of accurate reliability comparison of logic circuits, significantly reducing the number of simulations required to get an unambiguous solution.
KW - Gate failures
KW - Logic circuits
KW - Observability-based
KW - Reliability analysis
U2 - 10.1109/EIConRus.2017.7910618
DO - 10.1109/EIConRus.2017.7910618
M3 - Conference contribution
AN - SCOPUS:85019441423
T3 - Proceedings of the 2017 IEEE Russia Section Young Researchers in Electrical and Electronic Engineering Conference, ElConRus 2017
SP - 569
EP - 573
BT - Proceedings of the 2017 IEEE Russia Section Young Researchers in Electrical and Electronic Engineering Conference, ElConRus 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Russia Section Young Researchers in Electrical and Electronic Engineering Conference, ElConRus 2017
Y2 - 1 February 2017 through 3 February 2017
ER -