Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI

Francisco Veirano; Lirida Naviner; Fernando Silveira

doi:10.1109/PATMOS.2016.7833694

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI

Francisco Veirano
, Lirida Naviner
, Fernando Silveira

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.

Original language	English
Title of host publication	Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	243-249
Number of pages	7
ISBN (Electronic)	9781509007332
DOIs	https://doi.org/10.1109/PATMOS.2016.7833694
Publication status	Published - 25 Jan 2017
Externally published	Yes
Event	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 - Bremen, Germany Duration: 21 Sept 2016 → 23 Sept 2016

Publication series

Name	Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016

Conference

Conference	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Country/Territory	Germany
City	Bremen
Period	21/09/16 → 23/09/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/PATMOS.2016.7833694

Cite this

Veirano, F., Naviner, L., & Silveira, F. (2017). Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. In Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 (pp. 243-249). Article 7833694 (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PATMOS.2016.7833694

Veirano, Francisco ; Naviner, Lirida ; Silveira, Fernando. / Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 243-249 (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016).

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title = "Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI",

abstract = "In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30\% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.",

author = "Francisco Veirano and Lirida Naviner and Fernando Silveira",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 ; Conference date: 21-09-2016 Through 23-09-2016",

year = "2017",

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doi = "10.1109/PATMOS.2016.7833694",

language = "English",

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Veirano, F, Naviner, L & Silveira, F 2017, Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. in Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016., 7833694, Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 243-249, 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, 21/09/16. https://doi.org/10.1109/PATMOS.2016.7833694

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. / Veirano, Francisco; Naviner, Lirida; Silveira, Fernando.
Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 243-249 7833694 (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Naviner, Lirida

AU - Silveira, Fernando

PY - 2017/1/25

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N2 - In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.

AB - In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.

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Veirano F, Naviner L, Silveira F. Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. In Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 243-249. 7833694. (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016). doi: 10.1109/PATMOS.2016.7833694

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI

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