QSYN: Queueing networks synthesis for system on chip

O. Hammami

doi:10.1109/IDT.2008.4802458

QSYN: Queueing networks synthesis for system on chip

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Queueing networks represent a powerful model of computation (MOC) with strong theoretical foundations and a wide range of applications. Design productivity for system on chip (SOC) requires increasing the level of abstraction for the design of SOC. However, achieving better productivity through raising the level of abstraction can only be obtained with the help of automatic MOC transformation techniques. In this paper, we propose QSYN a tool for the automatic transformation of queueing network based MOC to an executable platform on FPGA. Case studies demonstrate the validity of our approach.

Original language	English
Title of host publication	Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008
Pages	22-27
Number of pages	6
DOIs	https://doi.org/10.1109/IDT.2008.4802458
Publication status	Published - 1 Dec 2008
Event	2008 3rd International Design and Test Workshop, IDT 2008 - Monastir, Tunisia Duration: 20 Dec 2008 → 22 Dec 2008

Publication series

Name	Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008

Conference

Conference	2008 3rd International Design and Test Workshop, IDT 2008
Country/Territory	Tunisia
City	Monastir
Period	20/12/08 → 22/12/08

Keywords

FPGA
MOC
Queueing network
SOC

Access to Document

10.1109/IDT.2008.4802458

Cite this

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title = "QSYN: Queueing networks synthesis for system on chip",

abstract = "Queueing networks represent a powerful model of computation (MOC) with strong theoretical foundations and a wide range of applications. Design productivity for system on chip (SOC) requires increasing the level of abstraction for the design of SOC. However, achieving better productivity through raising the level of abstraction can only be obtained with the help of automatic MOC transformation techniques. In this paper, we propose QSYN a tool for the automatic transformation of queueing network based MOC to an executable platform on FPGA. Case studies demonstrate the validity of our approach.",

keywords = "FPGA, MOC, Queueing network, SOC",

author = "O. Hammami",

year = "2008",

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language = "English",

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series = "Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008",

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note = "2008 3rd International Design and Test Workshop, IDT 2008 ; Conference date: 20-12-2008 Through 22-12-2008",

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Hammami, O 2008, QSYN: Queueing networks synthesis for system on chip. in Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008., 4802458, Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008, pp. 22-27, 2008 3rd International Design and Test Workshop, IDT 2008, Monastir, Tunisia, 20/12/08. https://doi.org/10.1109/IDT.2008.4802458

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QSYN: Queueing networks synthesis for system on chip

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Keywords

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