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Reconfigurable DSP architectures for SDR applications

  • Najam Ul Islam Muhammad
  • , Karim Khalfallah
  • , Raymond Knopp
  • , Renaud Pacalet
  • Eurecom

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

Addition of new bands, modes and services in mobile devices means the use of software defined radio (SDR) in the upcoming wireless devices is inevitable. To realize SDR, a common flexible hardware platform is required that supports transmission and reception of the existing radio access technologies. Air-interface and analog/digital conversions make a key part of SDR hardware both on transmitter and receiver. Front end processing block (FEP) of SDR consists of processing blocks required at the air-interface including Time/Frequency conversions, Dot-Products, Energy and Max calculations. We propose a flexible yet efficient hardware design for FEP that will furnish the front-end-functionality requirements of 2G, 3G, 4G, broadcast communication and wireless-LAN standards.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages971-974
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 2007 → 14 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/TerritoryMorocco
CityMarrakech
Period11/12/07 → 14/12/07

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