Abstract
Conventional approaches that have been used so far to implement powerful block-matching algorithms (BMAs) suffer from a serious limitation with regard to input data rate. In fact, as soon as the amount of data imported from the frame memory into the motion estimation chip exceeds a certain limit, these approaches fail in responding to the application specifications, either in terms of performance or cost-effectiveness. A new approach that considerably reduces the throughput rate is presented in this paper. It is more cost effective and performs much better than the conventional one when it comes to the implementation of multipredictive and multiresolution block-matching algorithms.
| Original language | English |
|---|---|
| Pages (from-to) | 249-252 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| Publication status | Published - 1 Jan 1996 |
| Event | Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: 12 May 1996 → 15 May 1996 |