Refresh-aware DDR3 barrel memory controller with deterministic functionality

With the increasing bandwidth demand in system technologies, several generations of memory have been optimized in order to guarantee higher QoS and better performance. Dynamic memory has various advantages in terms of frequency and bandwidth but the periodic refresh operation remains its principle weakness which reduces the chance of its use in reliable hardware real time systems. In spite of the refreshment important role to prevent data loss, this operation decreases predictability and bandwidth by about 3% in dynamic memories. We propose a memory controller which guarantees the refreshment of our DDR3 memory during the write operation. We choose to write in predefined address following a barrel shifter technique. This idea represents the key solution to visit all the rows within the maximum required refresh time. This technique is an original solution to preserve memory write, read and refresh reliability.