Regular 2D NASIC-based architecture and design space exploration

Ciprian Teodorov; Pritish Narayanan; Loic Lagadec; Catherine Dezan

doi:10.1109/NANOARCH.2011.5941486

Regular 2D NASIC-based architecture and design space exploration

Ciprian Teodorov
, Pritish Narayanan
, Loic Lagadec
, Catherine Dezan

ENSTA

University of Massachusetts
Université de Brest (UBO)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Citations (Scopus)

Abstract

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

Original language	English
Title of host publication	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Pages	70-77
Number of pages	8
DOIs	https://doi.org/10.1109/NANOARCH.2011.5941486
Publication status	Published - 11 Aug 2011
Event	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 - San Diego, CA, United States Duration: 8 Jun 2011 → 9 Jun 2011

Publication series

Name	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Conference

Conference	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Country/Territory	United States
City	San Diego, CA
Period	8/06/11 → 9/06/11

Access to Document

10.1109/NANOARCH.2011.5941486

Cite this

Teodorov, C., Narayanan, P., Lagadec, L., & Dezan, C. (2011). Regular 2D NASIC-based architecture and design space exploration. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 (pp. 70-77). Article 5941486 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). https://doi.org/10.1109/NANOARCH.2011.5941486

@inproceedings{ae2e6d1821a2497688507f2a52842125,

title = "Regular 2D NASIC-based architecture and design space exploration",

abstract = "As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.",

author = "Ciprian Teodorov and Pritish Narayanan and Loic Lagadec and Catherine Dezan",

year = "2011",

month = aug,

day = "11",

doi = "10.1109/NANOARCH.2011.5941486",

language = "English",

isbn = "9781457709944",

series = "Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011",

pages = "70--77",

booktitle = "Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011",

note = "2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 ; Conference date: 08-06-2011 Through 09-06-2011",

}

Teodorov, C, Narayanan, P, Lagadec, L & Dezan, C 2011, Regular 2D NASIC-based architecture and design space exploration. in Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011., 5941486, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, pp. 70-77, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, United States, 8/06/11. https://doi.org/10.1109/NANOARCH.2011.5941486

Regular 2D NASIC-based architecture and design space exploration. / Teodorov, Ciprian; Narayanan, Pritish; Lagadec, Loic et al.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 70-77 5941486 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Regular 2D NASIC-based architecture and design space exploration

AU - Teodorov, Ciprian

AU - Narayanan, Pritish

AU - Lagadec, Loic

AU - Dezan, Catherine

PY - 2011/8/11

Y1 - 2011/8/11

N2 - As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

AB - As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

UR - https://www.scopus.com/pages/publications/79961199570

U2 - 10.1109/NANOARCH.2011.5941486

DO - 10.1109/NANOARCH.2011.5941486

M3 - Conference contribution

AN - SCOPUS:79961199570

SN - 9781457709944

T3 - Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

SP - 70

EP - 77

BT - Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

T2 - 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Y2 - 8 June 2011 through 9 June 2011

ER -

Teodorov C, Narayanan P, Lagadec L, Dezan C. Regular 2D NASIC-based architecture and design space exploration. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 70-77. 5941486. (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). doi: 10.1109/NANOARCH.2011.5941486

Regular 2D NASIC-based architecture and design space exploration

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this