Relevant metrics for evaluation of concurrent error detection schemes

Concurrent error detection (CED) schemes are becoming essential features in the design process as IC technologies progress into the nanoscale era. Soft error rate reduction has emerged as an important challenge and several works are dedicated to quantify the CED effective enhancement in systems reliability. However, none of them make a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. Our experiments have shown that systems can reduce their throughput by half in multiple fault environments making the choice of the CED scheme strongly dependent on this analysis.