TY - GEN
T1 - Reliability analysis of a Reed-Solomon decoder
AU - Liu, Kaikai
AU - Ban, Tian
AU - Naviner, Lirida
AU - Naviner, Jean Francois
PY - 2012/10/16
Y1 - 2012/10/16
N2 - Due to the shrinking of dimension and decreasing of the supply voltage, processors based on deep submicron technologies are more susceptible to defects and errors. This paper presents a model to simulate the behavior of the Reed-Solomon decoder prone to transient faults. The simulation environment developed allows to analyze the influence of the different blocks on the reliability of the decoder. Identifying the most critical blocks of the processor allows the designer to implement a selective hardening strategy and then to minimize the additional costs associated to improve fault tolerance.
AB - Due to the shrinking of dimension and decreasing of the supply voltage, processors based on deep submicron technologies are more susceptible to defects and errors. This paper presents a model to simulate the behavior of the Reed-Solomon decoder prone to transient faults. The simulation environment developed allows to analyze the influence of the different blocks on the reliability of the decoder. Identifying the most critical blocks of the processor allows the designer to implement a selective hardening strategy and then to minimize the additional costs associated to improve fault tolerance.
U2 - 10.1109/MWSCAS.2012.6292051
DO - 10.1109/MWSCAS.2012.6292051
M3 - Conference contribution
AN - SCOPUS:84867298161
SN - 9781467325264
T3 - Midwest Symposium on Circuits and Systems
SP - 438
EP - 441
BT - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
T2 - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Y2 - 5 August 2012 through 8 August 2012
ER -