Reliability analysis of logic circuits based on signal probability

Denis Teixeira Franco; Mai Correia Vasconcelos; Lirida Naviner; Jean François Naviner

doi:10.1109/ICECS.2008.4674942

Reliability analysis of logic circuits based on signal probability

Denis Teixeira Franco, Mai Correia Vasconcelos, Lirida Naviner, Jean François Naviner

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on a four state representation of signal probabilities, and the propagation of this probabilities along the cells of a circuit, the signal reliability of the circuit can be directly obtained. The use of signal probabilities rises the well known problem of signals correlation, and we present some relaxing conditions that allow tradeoffs between accuracy and execution time of the algorithm. The main advantages of the proposed methodology are its simplicity and straightforward application, allowing an easy integration with design tools.

Original language	English
Title of host publication	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages	670-673
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2008.4674942
Publication status	Published - 26 Dec 2008
Externally published	Yes
Event	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta Duration: 31 Aug 2008 → 3 Sept 2008

Publication series

Name	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/Territory	Malta
City	St. Julian's
Period	31/08/08 → 3/09/08

Access to Document

10.1109/ICECS.2008.4674942

Cite this

Franco, D. T., Vasconcelos, M. C., Naviner, L., & Naviner, J. F. (2008). Reliability analysis of logic circuits based on signal probability. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 670-673). Article 4674942 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4674942

Franco, Denis Teixeira ; Vasconcelos, Mai Correia ; Naviner, Lirida et al. / Reliability analysis of logic circuits based on signal probability. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. pp. 670-673 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

@inproceedings{7d6715184b46457982de81078bd84a21,

title = "Reliability analysis of logic circuits based on signal probability",

abstract = "This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on a four state representation of signal probabilities, and the propagation of this probabilities along the cells of a circuit, the signal reliability of the circuit can be directly obtained. The use of signal probabilities rises the well known problem of signals correlation, and we present some relaxing conditions that allow tradeoffs between accuracy and execution time of the algorithm. The main advantages of the proposed methodology are its simplicity and straightforward application, allowing an easy integration with design tools.",

author = "Franco, \{Denis Teixeira\} and Vasconcelos, \{Mai Correia\} and Lirida Naviner and Naviner, \{Jean Fran{\c c}ois\}",

year = "2008",

month = dec,

day = "26",

doi = "10.1109/ICECS.2008.4674942",

language = "English",

isbn = "9781424421824",

series = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

pages = "670--673",

booktitle = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

note = "15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 ; Conference date: 31-08-2008 Through 03-09-2008",

}

Franco, DT, Vasconcelos, MC, Naviner, L & Naviner, JF 2008, Reliability analysis of logic circuits based on signal probability. in Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4674942, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pp. 670-673, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 31/08/08. https://doi.org/10.1109/ICECS.2008.4674942

Reliability analysis of logic circuits based on signal probability. / Franco, Denis Teixeira; Vasconcelos, Mai Correia; Naviner, Lirida et al.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 670-673 4674942 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reliability analysis of logic circuits based on signal probability

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AU - Vasconcelos, Mai Correia

AU - Naviner, Lirida

AU - Naviner, Jean François

PY - 2008/12/26

Y1 - 2008/12/26

N2 - This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on a four state representation of signal probabilities, and the propagation of this probabilities along the cells of a circuit, the signal reliability of the circuit can be directly obtained. The use of signal probabilities rises the well known problem of signals correlation, and we present some relaxing conditions that allow tradeoffs between accuracy and execution time of the algorithm. The main advantages of the proposed methodology are its simplicity and straightforward application, allowing an easy integration with design tools.

AB - This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on a four state representation of signal probabilities, and the propagation of this probabilities along the cells of a circuit, the signal reliability of the circuit can be directly obtained. The use of signal probabilities rises the well known problem of signals correlation, and we present some relaxing conditions that allow tradeoffs between accuracy and execution time of the algorithm. The main advantages of the proposed methodology are its simplicity and straightforward application, allowing an easy integration with design tools.

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DO - 10.1109/ICECS.2008.4674942

M3 - Conference contribution

AN - SCOPUS:57849112899

SN - 9781424421824

T3 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

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EP - 673

BT - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

T2 - 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Y2 - 31 August 2008 through 3 September 2008

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Franco DT, Vasconcelos MC, Naviner L, Naviner JF. Reliability analysis of logic circuits based on signal probability. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 670-673. 4674942. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). doi: 10.1109/ICECS.2008.4674942

Reliability analysis of logic circuits based on signal probability

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