Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power

Hao Cai; Menglin Han; You Wang; Lirida Naviner; Xinning Liu; Jun Yang; Weisheng Zhao

doi:10.1109/DCIS.2018.8681471

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power

Hao Cai
, Menglin Han
, You Wang
, Lirida Naviner
, Xinning Liu
, Jun Yang
, Weisheng Zhao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.

Original language	English
Title of host publication	Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728101712
DOIs	https://doi.org/10.1109/DCIS.2018.8681471
Publication status	Published - 3 Apr 2019
Externally published	Yes
Event	33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 - Lyon, France Duration: 14 Nov 2018 → 16 Nov 2018

Publication series

Name	Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018

Conference

Conference	33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018
Country/Territory	France
City	Lyon
Period	14/11/18 → 16/11/18

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/DCIS.2018.8681471

Cite this

Cai, H., Han, M., Wang, Y., Naviner, L., Liu, X., Yang, J., & Zhao, W. (2019). Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. In Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 Article 8681471 (Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DCIS.2018.8681471

@inproceedings{8aa78bbdf3804671ae6f7d0ea0c66660,

title = "Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power",

abstract = "An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.",

author = "Hao Cai and Menglin Han and You Wang and Lirida Naviner and Xinning Liu and Jun Yang and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 ; Conference date: 14-11-2018 Through 16-11-2018",

year = "2019",

month = apr,

day = "3",

doi = "10.1109/DCIS.2018.8681471",

language = "English",

series = "Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018",

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booktitle = "Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018",

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Cai, H, Han, M, Wang, Y, Naviner, L, Liu, X, Yang, J & Zhao, W 2019, Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. in Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018., 8681471, Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018, Institute of Electrical and Electronics Engineers Inc., 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, 14/11/18. https://doi.org/10.1109/DCIS.2018.8681471

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. / Cai, Hao; Han, Menglin; Wang, You et al.
Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8681471 (Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power

AU - Cai, Hao

AU - Han, Menglin

AU - Wang, You

AU - Naviner, Lirida

AU - Liu, Xinning

AU - Yang, Jun

AU - Zhao, Weisheng

PY - 2019/4/3

Y1 - 2019/4/3

N2 - An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.

AB - An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.

UR - https://www.scopus.com/pages/publications/85064686091

U2 - 10.1109/DCIS.2018.8681471

DO - 10.1109/DCIS.2018.8681471

M3 - Conference contribution

AN - SCOPUS:85064686091

T3 - Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018

BT - Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018

Y2 - 14 November 2018 through 16 November 2018

ER -

Cai H, Han M, Wang Y, Naviner L, Liu X, Yang J et al. Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. In Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8681471. (Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018). doi: 10.1109/DCIS.2018.8681471

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power

Abstract

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