@inproceedings{b5c0bd21b37a4761a8016f7764e2110f,
title = "Reliability evaluation of circuits designed in multi-and single-stage versions",
abstract = "Nanometer circuits suffer heavily from fabrication, transient and permanent failures. Circuit reliability has to be added to the design space. Probabilistic transfer matrix is an exact method to calculate the reliability of a circuit. Traditionally, logic gates are the basic blocks of this method with a constant reliability for all gates and all possible input vector combination. This paper introduces the importance of considering the transistor arrangement as a pre-processing step and presents an analysis of logic functions designed in single-and multi-stage versions. The results show that single-stage versions present higher reliability when compared to the multi-stage solution. These results confirm the higher robustness induced by more complex arrangements.",
keywords = "CMOS, Digital ICs, Reliability",
author = "Schvittz, \{R. B.\} and M. Pontes and C. Meinhardt and Franco, \{D. T.\} and L. Naviner and \{Da Rosa\}, \{L. S.\} and Butzen, \{P. F.\}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 9th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2018 ; Conference date: 25-02-2018 Through 28-02-2018",
year = "2018",
month = jun,
day = "28",
doi = "10.1109/LASCAS.2018.8399927",
language = "English",
series = "9th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--4",
booktitle = "9th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2018 - Proceedings",
}