TY - GEN
T1 - Reliability of logic circuits under multiple simultaneous faults
AU - Franco, Denis Teixeira
AU - Vasconcelos, Maǐ Correia
AU - Naviner, Lirida
AU - Naviner, Jean François
PY - 2008/10/27
Y1 - 2008/10/27
N2 - The reliability of integrated circuits has become an unavoidable subject in the nanoscale era. The susceptibility of combinational logic circuits to faults is of increasing interest, and fast and accurate methods are necessary to take the reliability into account earlier in the design process. As circuits scale to nanometer dimensions, the probability of occurrence of multiple simultaneous faults becomes higher and cannot be neglected anymore. In this work, a signal probability reliability analysis (SPRA) algorithm is presented, allowing an evaluation of the reliability of logic circuits relating to multiple simultaneous faults.
AB - The reliability of integrated circuits has become an unavoidable subject in the nanoscale era. The susceptibility of combinational logic circuits to faults is of increasing interest, and fast and accurate methods are necessary to take the reliability into account earlier in the design process. As circuits scale to nanometer dimensions, the probability of occurrence of multiple simultaneous faults becomes higher and cannot be neglected anymore. In this work, a signal probability reliability analysis (SPRA) algorithm is presented, allowing an evaluation of the reliability of logic circuits relating to multiple simultaneous faults.
U2 - 10.1109/MWSCAS.2008.4616787
DO - 10.1109/MWSCAS.2008.4616787
M3 - Conference contribution
AN - SCOPUS:54249166308
SN - 9781424421671
T3 - Midwest Symposium on Circuits and Systems
SP - 265
EP - 268
BT - 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
T2 - 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Y2 - 10 August 2008 through 13 August 2008
ER -