Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

Hao Cai; You Wang; Lirida Alves De Barros Naviner; Weisheng Zhao

doi:10.1109/TCSI.2016.2621344

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

Hao Cai, You Wang, Lirida Alves De Barros Naviner, Weisheng Zhao

Research output: Contribution to journal › Article › peer-review

Abstract

In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (V_dd) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome V_dd scaling bottleneck, an efficient framework for V_dd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (V_dd, V_BB,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.

Original language	English
Article number	7748536
Pages (from-to)	847-857
Number of pages	11
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	64
Issue number	4
DOIs	https://doi.org/10.1109/TCSI.2016.2621344
Publication status	Published - 1 Apr 2017
Externally published	Yes

Keywords

FD-SOI
MTJ
Non-volatile logic-in-memory (NV-LIM)
approximate computing
ultra-low power

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10.1109/TCSI.2016.2621344

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title = "Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology",

abstract = "In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (Vdd) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome Vdd scaling bottleneck, an efficient framework for Vdd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (Vdd, VBB,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.",

keywords = "FD-SOI, MTJ, Non-volatile logic-in-memory (NV-LIM), approximate computing, ultra-low power",

author = "Hao Cai and You Wang and \{De Barros Naviner\}, \{Lirida Alves\} and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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doi = "10.1109/TCSI.2016.2621344",

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PY - 2017/4/1

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N2 - In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (Vdd) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome Vdd scaling bottleneck, an efficient framework for Vdd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (Vdd, VBB,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.

AB - In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (Vdd) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome Vdd scaling bottleneck, an efficient framework for Vdd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (Vdd, VBB,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.

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ER -

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

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