SDR waveform components implementation on single FPGA multiprocessor platform

M. I. Taj, O. Hammami, M. Akil

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Multiprocessors in embedded systems have a bright future with Software Defined Radio (SDR) applications where both, high performance and high adaptability are required. Framed within this statement, this paper implements the two most important SDR waveform components: FFT and Viterbi Decoding, on our designed 16 Processing Element (PE) Network on chip (NoC) based general purpose Multiprocessors System on chip (MPSoC), implemented on a single chip Xilinx Virtex-4 FPGA. We designed a parallelization strategy, by synchronizing the PEs, for each of the two algorithms and obtained a speed-up of 6 with eight PEs, for radix-2 FFT and 216 states of Viterbi Decoding. We also propose partitioning mechanism for SDR resources for PEs more than eight. The case study of our partitioning mechanism reduced execution time to 63%, thus an efficient answer to ITRS prediction.

Original languageEnglish
Title of host publication2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings
Pages790-793
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2010
Event2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Athens, Greece
Duration: 12 Dec 201015 Dec 2010

Publication series

Name2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings

Conference

Conference2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010
Country/TerritoryGreece
CityAthens
Period12/12/1015/12/10

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