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Soft timing closure for soft programmable logic cores: The ARGen approach

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  • IRISA

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits’ lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerbating timing closure issues. This article tackles these two issues and introduces the ARGen generator that produces scalable soft reconfigurable cores. The architectural template relies on injecting flipflops into the interconnect, to favor easy and accurate timing estimation. The cores are compliant with the academic standard for place and route environment, making ARGen a one stop shopping point for whoever needs exploitable soft reconfigurable cores.

Original languageEnglish
Title of host publicationApplied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings
EditorsAntonio Carlos Beck, Luigi Carro , Stephan Wong, Koen Bertels
PublisherSpringer Verlag
Pages93-105
Number of pages13
ISBN (Print)9783319562575
DOIs
Publication statusPublished - 1 Jan 2017
Event13th International Symposium on Applied Reconfigurable Computing, ARC 2017 - Delft, Netherlands
Duration: 3 Apr 2017 → 7 Apr 2017

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume10216 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference13th International Symposium on Applied Reconfigurable Computing, ARC 2017
Country/TerritoryNetherlands
City Delft
Period3/04/17 → 7/04/17

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