SOM on multi-FPGA ISA board-hardware aspects

D. Suzuki; O. Hammami

doi:10.1109/ICECS.1999.814431

SOM on multi-FPGA ISA board-hardware aspects

D. Suzuki, O. Hammami

Univ of Aizu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.

Original language	English
Title of host publication	Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1401-1405
Number of pages	5
ISBN (Electronic)	0780356829
DOIs	https://doi.org/10.1109/ICECS.1999.814431
Publication status	Published - 1 Jan 1999
Externally published	Yes
Event	6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 - Pafos, Cyprus Duration: 5 Sept 1999 → 8 Sept 1999

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	3

Conference

Conference	6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999
Country/Territory	Cyprus
City	Pafos
Period	5/09/99 → 8/09/99

Access to Document

10.1109/ICECS.1999.814431

Cite this

Suzuki, D., & Hammami, O. (1999). SOM on multi-FPGA ISA board-hardware aspects. In Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems (pp. 1401-1405). Article 814431 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1999.814431

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title = "SOM on multi-FPGA ISA board-hardware aspects",

abstract = "This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.",

author = "D. Suzuki and O. Hammami",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 ; Conference date: 05-09-1999 Through 08-09-1999",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/ICECS.1999.814431",

language = "English",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

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Suzuki, D & Hammami, O 1999, SOM on multi-FPGA ISA board-hardware aspects. in Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems., 814431, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1401-1405, 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, 5/09/99. https://doi.org/10.1109/ICECS.1999.814431

SOM on multi-FPGA ISA board-hardware aspects. / Suzuki, D.; Hammami, O.
Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 1999. p. 1401-1405 814431 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hammami, O.

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N2 - This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.

AB - This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.

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BT - Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 5 September 1999 through 8 September 1999

ER -

Suzuki D, Hammami O. SOM on multi-FPGA ISA board-hardware aspects. In Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 1999. p. 1401-1405. 814431. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.1999.814431

SOM on multi-FPGA ISA board-hardware aspects

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