Studies of the stability of microcrystalline silicon bottom-gate TFTs under electrical stress

We present, in this paper, the stability results under bias stress of n-type microcrystalline silicon (μc-Si:H) bottom- gate thin- film transistors (TFTs) with various intrinsic layer compositions (a single μc-Si layer or a dual intrinsic layer made of a-Si:H and μc-Si). TFTs were fabricated using the conventional amorphous silicon (a-Si:H) TFT process (low temperature Plasma Enhanced Chemical Vapor Deposition). Our results suggest that the dual layer structure is advantageous in terms of processing while keeping good mobility and stability. After 24 hr of electrical stress the threshold voltage drift (ΔVr) was less than 0.2 V and mobility drift (Δμ) was about 8%. In order to understand the causes of the instability, experimental analyses were performed; they showed that charge trapping at the interface was responsible for the degradation in the TFTs. Simulation of the impact of threshold voltage (V_T) and the mobility drifts showed that a 1-V variation in V _T induced a variation of 36% in OLED current and that a variation of 20% in the mobility leads to a 23% variation in the OLED current.