Abstract
We have previously shown from static planar conductance measurements that a strong inversion layer does exist in c-Si at the (n) a-Si:H/ (p) c-Si interface. This allowed us to determine the conduction band offset with a good precision (ΔEC = 0.15 +/- 0.04 eV). The same technique is now applied to study (p) a-Si:H/ (n) c-Si interfaces. We demonstrate that a strong inversion layer (of holes) also exists at the c-Si surface of this hetero-interface. Analysis of our planar conductance data with the help of numerical simulations allows us to set a lower limit to the valence band offset, ΔEV = EV,a-Si:H - EV, c-Si : ΔEV> 0.28 eV.
| Original language | English |
|---|---|
| Pages (from-to) | 1037-1040 |
| Number of pages | 4 |
| Journal | Physica Status Solidi (C) Current Topics in Solid State Physics |
| Volume | 7 |
| Issue number | 3-4 |
| DOIs | |
| Publication status | Published - 1 Jan 2010 |
| Event | 23rd International Conference on Amorphous and Nanocrystalline Semiconductors, ICANS23 - Utrecht, Netherlands Duration: 23 Aug 2009 → 28 Aug 2009 |
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