System Design for Direct RF-to-Digital σ Receiver

The Direct RF-to-Digital ΔΣ receiver has emerged as an attractive solution for multi-band multi-standard wireless applications. This architecture is a direct RF to baseband digitizer with RF feedback from baseband to RF stages. The presence of the RF blocks such as the low noise amplifier and down-conversion mixer inside the loop filter significantly relaxes their linearity requirements and also improves the noise transfer function of the loop filter. However, the RF feedback poses several challenges, especially making the design methodology more complex. In contrast to classical receiver architectures, the blocks of the Direct RF-to-Digital ΔΣ receiver cannot be designed, analyzed, and simulated independently. Besides, conventional design methodologies for ΔΣ Modulators cannot be applied for this kind of receiver due to the presence of the RF blocks and the RF feedback inside the loop. This paper presents a new design methodology suited for this family of receivers. The proposed methodology covers simulation approaches, system design, and non-ideality impacts on the receiver. A design example of a multi-band multi-standard receiver for GSM/WCDMA/LTE is considered throughout the paper to demonstrate this design methodology.