System-level design methodology with direct execution for multiprocessors on SoPC

Contrary to ASIC design where resources can be tuned with respect to the need of the designer, systems on programmable chip SoPC (FPGA) have to make best use of 'off the shelf devices', where main resources are fixed. In this regard, embedded memories are of tremendous value because of their low latency. These embedded memories are not only used for data and program storage but also for all sorts of memory usage e.g. FIFO used by IP interfaces for bus and network on chip connection. The problem addressed by this paper is the optimal sizing of queues in the framework of SoPC. Current SoC design tools are of little help to define the most adequate size for these FIFOs and the large design space coupled with excessive simulation times make it even more difficult. We propose in this paper an automatic tuning technique of queue sizes in IP interfaces for system on programmable chip with hardware in the loop execution. An application of our technique on Virtex-II SoPC is described.