TY - GEN
T1 - Test derivation for SDN-enabled switches
T2 - 30th IFIP International Conference on Testing Software and Systems, ICTSS 2018
AU - López, Jorge
AU - Kushik, Natalia
AU - Berriri, Asma
AU - Yevtushenko, Nina
AU - Zeghlache, Djamal
N1 - Publisher Copyright:
© IFIP International Federation for Information Processing 2018.
PY - 2018/1/1
Y1 - 2018/1/1
N2 - The paper is devoted to testing critical Software Defined Networking (SDN) components and in particular, SDN-enabled switches. A switch can be seen as a forwarding device with a set of configured rules and thus, can be modelled and analyzed as a ‘stateless’ system. Correspondingly, in this paper we propose to use appropriate logic circuits or networks to model the switch behavior. Both active and passive testing modes can benefit from such representation. First, this allows applying well-known test generation strategies such as for example, test derivation techniques targeting Single Stuck-at Faults (SSFs). We also specify a number of mutation operators for switch rules and propose an algorithm for eliminating equivalent mutants via SAT solving. Logic circuits simulating the behavior of the switches can be effectively utilized for run-time verification, and such logic circuit based approach is also discussed in the paper. Preliminary experimental results with Open vSwitch, on one hand, demonstrate the necessity of considering new fault models for logic circuits (apart from, for example well established SSFs) and on the other hand, confirm the efficiency of the proposed test generation and verification techniques.
AB - The paper is devoted to testing critical Software Defined Networking (SDN) components and in particular, SDN-enabled switches. A switch can be seen as a forwarding device with a set of configured rules and thus, can be modelled and analyzed as a ‘stateless’ system. Correspondingly, in this paper we propose to use appropriate logic circuits or networks to model the switch behavior. Both active and passive testing modes can benefit from such representation. First, this allows applying well-known test generation strategies such as for example, test derivation techniques targeting Single Stuck-at Faults (SSFs). We also specify a number of mutation operators for switch rules and propose an algorithm for eliminating equivalent mutants via SAT solving. Logic circuits simulating the behavior of the switches can be effectively utilized for run-time verification, and such logic circuit based approach is also discussed in the paper. Preliminary experimental results with Open vSwitch, on one hand, demonstrate the necessity of considering new fault models for logic circuits (apart from, for example well established SSFs) and on the other hand, confirm the efficiency of the proposed test generation and verification techniques.
KW - Logic circuits
KW - Mutation testing
KW - Run-time verification
KW - SDN-enabled switches
KW - Software defined networking (SDN)
U2 - 10.1007/978-3-319-99927-2_7
DO - 10.1007/978-3-319-99927-2_7
M3 - Conference contribution
AN - SCOPUS:85053878853
SN - 9783319999265
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 69
EP - 84
BT - Testing Software and Systems - 30th IFIP WG 6.1 International Conference, ICTSS 2018, Proceedings
A2 - Medina-Bulo, Inmaculada
A2 - Merayo, Mercedes G.
A2 - Hierons, Robert
PB - Springer Verlag
Y2 - 1 October 2018 through 3 October 2018
ER -