Test sequence generation from formally verified sysml models

Pierre De Saqui-Sannes, Ludovic Apvrille

Research output: Contribution to journalConference articlepeer-review

Abstract

Test generation has been acknowledged as a costprone activity reducing productivity and time to market. The expected benefits of Model Based Systems Engineering include automated generation of test sequences from models. The paper proposes verification solutions for the System Modeling Language (SysML). In particular, the paper shows how to link test generation to formal verification. The proposed algorithms are implemented by the free software TTool. Two case studies support discussion on conformance and interoperability testing, respectively.

Original languageEnglish
Pages (from-to)67-74
Number of pages8
JournalCEUR Workshop Proceedings
Volume2308
Publication statusPublished - 1 Jan 2019
Externally publishedYes
Event2019 Workshops of the Software Engineering Conference, SEW 2019 - Stuttgart, Germany
Duration: 18 Feb 201922 Feb 2019

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