Testing logic circuits at different abstraction levels: An experimental evaluation

Sergey Smolov; Jorge Lopez; Natalia Kushik; Nina Yevtushenko; Mikhail Chupilko; Alexander Kamkin

doi:10.1109/EWDTS.2016.7807687

Testing logic circuits at different abstraction levels: An experimental evaluation

Sergey Smolov
, Jorge Lopez
, Natalia Kushik
, Nina Yevtushenko
, Mikhail Chupilko
, Alexander Kamkin

Ivannikov Institute for System Programming of the RAS
Tomsk State University
Université Paris-Saclay

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones.

Original language	English
Title of host publication	Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509006939
DOIs	https://doi.org/10.1109/EWDTS.2016.7807687
Publication status	Published - 1 Jan 2016
Externally published	Yes
Event	2016 IEEE East-West Design and Test Symposium, EWDTS 2016 - Yerevan, Armenia Duration: 14 Oct 2016 → 17 Oct 2016

Publication series

Name	Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016

Conference

Conference	2016 IEEE East-West Design and Test Symposium, EWDTS 2016
Country/Territory	Armenia
City	Yerevan
Period	14/10/16 → 17/10/16

Access to Document

10.1109/EWDTS.2016.7807687

Cite this

Smolov, S., Lopez, J., Kushik, N., Yevtushenko, N., Chupilko, M., & Kamkin, A. (2016). Testing logic circuits at different abstraction levels: An experimental evaluation. In Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016 Article 7807687 (Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EWDTS.2016.7807687

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title = "Testing logic circuits at different abstraction levels: An experimental evaluation",

abstract = "The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones.",

author = "Sergey Smolov and Jorge Lopez and Natalia Kushik and Nina Yevtushenko and Mikhail Chupilko and Alexander Kamkin",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE East-West Design and Test Symposium, EWDTS 2016 ; Conference date: 14-10-2016 Through 17-10-2016",

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doi = "10.1109/EWDTS.2016.7807687",

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Smolov, S, Lopez, J, Kushik, N, Yevtushenko, N, Chupilko, M & Kamkin, A 2016, Testing logic circuits at different abstraction levels: An experimental evaluation. in Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016., 7807687, Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE East-West Design and Test Symposium, EWDTS 2016, Yerevan, Armenia, 14/10/16. https://doi.org/10.1109/EWDTS.2016.7807687

Testing logic circuits at different abstraction levels: An experimental evaluation. / Smolov, Sergey; Lopez, Jorge; Kushik, Natalia et al.
Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7807687 (Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chupilko, Mikhail

AU - Kamkin, Alexander

PY - 2016/1/1

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AB - The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones.

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M3 - Conference contribution

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Smolov S, Lopez J, Kushik N, Yevtushenko N, Chupilko M, Kamkin A. Testing logic circuits at different abstraction levels: An experimental evaluation. In Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7807687. (Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016). doi: 10.1109/EWDTS.2016.7807687

Testing logic circuits at different abstraction levels: An experimental evaluation

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