TY - GEN
T1 - Testing logic circuits at different abstraction levels
T2 - 2016 IEEE East-West Design and Test Symposium, EWDTS 2016
AU - Smolov, Sergey
AU - Lopez, Jorge
AU - Kushik, Natalia
AU - Yevtushenko, Nina
AU - Chupilko, Mikhail
AU - Kamkin, Alexander
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/1/1
Y1 - 2016/1/1
N2 - The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones.
AB - The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones.
U2 - 10.1109/EWDTS.2016.7807687
DO - 10.1109/EWDTS.2016.7807687
M3 - Conference contribution
AN - SCOPUS:85015223015
T3 - Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016
BT - Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 14 October 2016 through 17 October 2016
ER -