Transient fault analysis of CORDIC processor

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we propose a method to evaluate the impact of a transient fault in CORDIC processors. The proposed approach takes into account the spatial and temporal localization of the fault. It also embeds the probability that such a fault occurs. By defining a fault impact coefficient, it is possible to identify the most critical arithmetic blocks and thus to implement an optimized strategy for fault tolerance. We analyzed two structures of CORDIC processors and we showed how to get a better tradeoff between the penalty (area and delay overhead) and the fault tolerant improvement.

Original languageEnglish
Title of host publication2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Pages757-760
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2012
Externally publishedYes
Event2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 - Seville, Seville, Spain
Duration: 9 Dec 201212 Dec 2012

Publication series

Name2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Conference

Conference2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Country/TerritorySpain
CitySeville, Seville
Period9/12/1212/12/12

Keywords

  • Arithmetic Operators
  • CORDIC
  • Fault-tolerance
  • Selective-Hardening
  • Transient Fault

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