VLSI architecture for image geometrical transformations using an embedded core based processor

Carolina Miro; Nicolas Darbel; Renaud Pacalet; Valerie Paquet

VLSI architecture for image geometrical transformations using an embedded core based processor

Carolina Miro
, Nicolas Darbel
, Renaud Pacalet
, Valerie Paquet

Telecom Paris

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.

Original language	English
Pages	86-95
Number of pages	10
Publication status	Published - 1 Jan 1997
Event	Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 - Zurich, Switz Duration: 14 Jul 1997 → 16 Jul 1997

Conference

Conference	Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97
City	Zurich, Switz
Period	14/07/97 → 16/07/97

Cite this

@conference{4d8bf84d6ddc4de8839c0c8f73aef3aa,

title = "VLSI architecture for image geometrical transformations using an embedded core based processor",

abstract = "This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.",

author = "Carolina Miro and Nicolas Darbel and Renaud Pacalet and Valerie Paquet",

year = "1997",

month = jan,

day = "1",

language = "English",

pages = "86--95",

note = "Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 ; Conference date: 14-07-1997 Through 16-07-1997",

}

VLSI architecture for image geometrical transformations using an embedded core based processor. / Miro, Carolina; Darbel, Nicolas; Pacalet, Renaud et al.
1997. 86-95 Paper presented at Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97, Zurich, Switz.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - VLSI architecture for image geometrical transformations using an embedded core based processor

AU - Miro, Carolina

AU - Darbel, Nicolas

AU - Pacalet, Renaud

AU - Paquet, Valerie

PY - 1997/1/1

Y1 - 1997/1/1

N2 - This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.

AB - This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.

M3 - Paper

AN - SCOPUS:0030689601

SP - 86

EP - 95

T2 - Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97

Y2 - 14 July 1997 through 16 July 1997

ER -

VLSI architecture for image geometrical transformations using an embedded core based processor

Abstract

Conference

Fingerprint

Cite this