Yield and reliability issues in nanoelectronic technologies

Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that follow the rates predicted in Moore's law. The tradeoffs in area, speed and power, allowed by the CMOS technology, and its capacity to integrate analog, digital and mixed components, arc key features to its dissemination in the telecommunications field. In fact, the progress of the CMOS technology is an important driver for telecommunications evolution, with the continuous integration of complex functions needed by demanding applications. As integrated circuits evolve, they approach some limits that make further improvements more difficult and even unpredictable. With deep-submicron structures, the yield of manufacturing processes is one of the main challenges of the semiconductor industry, with negative impacts on time-to-market and profitability. With reduced voltages and increased speed and density, the reliability of deep-submicron circuits is another concern for designers, since noise immunity is reduced and thermal noise effects show-up. In this paper we present an overview of the issues related with the scaling of integrated circuits into nanometer technologies, detailing the yield and reliability problems. We present the state of the art in proposed solutions and alternatives that can improve the chances of a large utilization of these nanotechnologies.