TY - GEN
T1 - A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC
AU - Jabbour, Chadi
AU - Camarero, David
AU - Van, Tam Nguyen
AU - Loumeau, Patrick
PY - 2009/10/26
Y1 - 2009/10/26
N2 - This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΔΣ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm 2.
AB - This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΔΣ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm 2.
UR - https://www.scopus.com/pages/publications/70350154566
U2 - 10.1109/ISCAS.2009.5118066
DO - 10.1109/ISCAS.2009.5118066
M3 - Conference contribution
AN - SCOPUS:70350154566
SN - 9781424438280
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1557
EP - 1560
BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Y2 - 24 May 2009 through 27 May 2009
ER -