A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor

Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Ville Yli-Mayry; Naofumi Homma; Yves Mathieu; Tarik Graba; Jean Luc Danger

doi:10.23919/VLSIC.2017.8008502

A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor

Noriyuki Miura
, Kohei Matsuda
, Makoto Nagata
, Shivam Bhasin
, Ville Yli-Mayry
, Naofumi Homma
, Yves Mathieu
, Tarik Graba
, Jean Luc Danger

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

langue originale	Anglais
titre	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Editeur	Institute of Electrical and Electronics Engineers Inc.
Pages	C266-C267
ISBN (Electronique)	9784863486065
Les DOIs	https://doi.org/10.23919/VLSIC.2017.8008502
état	Publié - 10 août 2017
Evénement	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japon Durée: 5 juin 2017 → 8 juin 2017

Série de publications

Nom	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Une conférence

Une conférence	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Pays/Territoire	Japon
La ville	Kyoto
période	5/06/17 → 8/06/17

Accès au document

10.23919/VLSIC.2017.8008502

Autres fichiers et liens

Lien vers la publication dans Scopus

Contient cette citation

Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Yli-Mayry, V., Homma, N., Mathieu, Y., Graba, T., & Danger, J. L. (2017). A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. Dans 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (p. C266-C267). Article 8008502 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008502

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title = "A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor",

abstract = "An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.",

author = "Noriyuki Miura and Kohei Matsuda and Makoto Nagata and Shivam Bhasin and Ville Yli-Mayry and Naofumi Homma and Yves Mathieu and Tarik Graba and Danger, \{Jean Luc\}",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 31st Symposium on VLSI Circuits, VLSI Circuits 2017 ; Conference date: 05-06-2017 Through 08-06-2017",

year = "2017",

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doi = "10.23919/VLSIC.2017.8008502",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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Miura, N, Matsuda, K, Nagata, M, Bhasin, S, Yli-Mayry, V, Homma, N, Mathieu, Y, Graba, T & Danger, JL 2017, A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. Dans 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008502, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., p. C266-C267, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japon, 5/06/17. https://doi.org/10.23919/VLSIC.2017.8008502

A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. / Miura, Noriyuki; Matsuda, Kohei; Nagata, Makoto et al.
2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C266-C267 8008502 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

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AU - Bhasin, Shivam

AU - Yli-Mayry, Ville

AU - Homma, Naofumi

AU - Mathieu, Yves

AU - Graba, Tarik

AU - Danger, Jean Luc

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N2 - An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

AB - An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

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BT - 2017 Symposium on VLSI Circuits, VLSI Circuits 2017

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Miura N, Matsuda K, Nagata M, Bhasin S, Yli-Mayry V, Homma N et al. A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. Dans 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C266-C267. 8008502. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2017.8008502