TY - GEN
T1 - A dual threshold voltage technique for glitch minimization
AU - Slimani, Mariem
AU - Matherat, Philippe
AU - Mathieu, Yves
PY - 2012/12/1
Y1 - 2012/12/1
N2 - We propose to use dual-threshold voltage (dual-Vth) assignment for glitch reduction. We present a heuristic algorithm address this problem. Experimental results on 6 ISCAS85 benchmark circuits implemented in a 65 nm industrial low power CMOS process report more than 16% of glitch reduction on average, and up to 41% for C432 benchmark circuit. To further minimize glitches, we propose to unify gate-sizing and dual-Vth techniques into a single optimization process. Results show an improvement of 10% on average compared to the conventional gate-sizing method. Spice simulations of C432 benchmark circuit report more than 27% and 48% total energy reduction by means the proposed dual-Vth and dual-Vth/gate-sizing algorithm, respectively.
AB - We propose to use dual-threshold voltage (dual-Vth) assignment for glitch reduction. We present a heuristic algorithm address this problem. Experimental results on 6 ISCAS85 benchmark circuits implemented in a 65 nm industrial low power CMOS process report more than 16% of glitch reduction on average, and up to 41% for C432 benchmark circuit. To further minimize glitches, we propose to unify gate-sizing and dual-Vth techniques into a single optimization process. Results show an improvement of 10% on average compared to the conventional gate-sizing method. Spice simulations of C432 benchmark circuit report more than 27% and 48% total energy reduction by means the proposed dual-Vth and dual-Vth/gate-sizing algorithm, respectively.
KW - Circuit-level Design
KW - Glitch power reduction
KW - threshold voltage variation
U2 - 10.1109/ICECS.2012.6463554
DO - 10.1109/ICECS.2012.6463554
M3 - Conference contribution
AN - SCOPUS:84874601611
SN - 9781467312615
T3 - 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
SP - 444
EP - 447
BT - 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
T2 - 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Y2 - 9 December 2012 through 12 December 2012
ER -