TY - GEN
T1 - A flexible receiver using ΔΣ modulation
AU - Nguyen, Minh Tien
AU - Jabbour, Chadi
AU - Nguyen, Van Tam
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/29
Y1 - 2016/7/29
N2 - This paper presents a reconfigurable 2nd/3rd-order discrete-time direct RF-to-digital ΔΣ receiver architecture for wide frequency range flexible receivers. Using 25% duty-cycle current-driven passive mixer along with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement on LNTA. Moreover, the passive/active implementation of the loop filter gives a good trade-off between power consumption, linearity and dynamic range. A design example with 10 MHz useful bandwidth and 0.4-4.0 GHz frequency range is conducted to demonstrate the feasibility and the characteristics of this proposed architecture.
AB - This paper presents a reconfigurable 2nd/3rd-order discrete-time direct RF-to-digital ΔΣ receiver architecture for wide frequency range flexible receivers. Using 25% duty-cycle current-driven passive mixer along with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement on LNTA. Moreover, the passive/active implementation of the loop filter gives a good trade-off between power consumption, linearity and dynamic range. A design example with 10 MHz useful bandwidth and 0.4-4.0 GHz frequency range is conducted to demonstrate the feasibility and the characteristics of this proposed architecture.
UR - https://www.scopus.com/pages/publications/84983412358
U2 - 10.1109/ISCAS.2016.7527535
DO - 10.1109/ISCAS.2016.7527535
M3 - Conference contribution
AN - SCOPUS:84983412358
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1470
EP - 1473
BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Y2 - 22 May 2016 through 25 May 2016
ER -