TY - GEN
T1 - A hybrid reliability assessment method and its support of sequential logic modelling
AU - Pagliarini, Samuel N.
AU - De Naviner, Lirida A.B.
AU - Naviner, Jean Francois
AU - Pradhan, Dhiraj
PY - 2014/1/1
Y1 - 2014/1/1
N2 - This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.
AB - This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.
U2 - 10.1109/IOLTS.2014.6873690
DO - 10.1109/IOLTS.2014.6873690
M3 - Conference contribution
AN - SCOPUS:84906656840
SN - 9781479953233
T3 - Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014
SP - 182
EP - 183
BT - Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014
PB - IEEE Computer Society
T2 - 20th IEEE International On-Line Testing Symposium, IOLTS 2014
Y2 - 7 July 2014 through 9 July 2014
ER -