TY - GEN
T1 - A low cost reliable architecture for S-Boxes in AES processors
AU - An, Ting
AU - Naviner, Lirida Alves De Barros
AU - Matherat, Philippe
PY - 2013/12/1
Y1 - 2013/12/1
N2 - This paper presents a fault-tolerant architecture for AES processors in order to mitigate the reliability issues introduced by the continued shrinking of CMOS technology. We concentrate on the faults occurring on S-Boxes which consume the largest hardware in AES processor. This hybrid solution combines time redundancy and hardware redundancy strategies for masking all single transient and permanent faults. By exploiting the inherent redundancy of AES processor with parallel implementation, the proposed solution limits the area overhead and overcomes many popular fault-tolerant techniques such as Triple Modular Redundancy approach and Triple Temporal Redundancy approaches.
AB - This paper presents a fault-tolerant architecture for AES processors in order to mitigate the reliability issues introduced by the continued shrinking of CMOS technology. We concentrate on the faults occurring on S-Boxes which consume the largest hardware in AES processor. This hybrid solution combines time redundancy and hardware redundancy strategies for masking all single transient and permanent faults. By exploiting the inherent redundancy of AES processor with parallel implementation, the proposed solution limits the area overhead and overcomes many popular fault-tolerant techniques such as Triple Modular Redundancy approach and Triple Temporal Redundancy approaches.
UR - https://www.scopus.com/pages/publications/84891336732
U2 - 10.1109/DFT.2013.6653599
DO - 10.1109/DFT.2013.6653599
M3 - Conference contribution
AN - SCOPUS:84891336732
SN - 9781479915835
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 155
EP - 160
BT - Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
T2 - 2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
Y2 - 2 October 2013 through 4 October 2013
ER -