TY - GEN
T1 - A method for efficient implementation of reliable processors
AU - Marques, Elaine C.
AU - Naviner, Lirida A.B.
AU - Naviner, Jean François
PY - 2010/9/20
Y1 - 2010/9/20
N2 - Reliability is becoming an important feature of digital circuits implemented on deep submicron technologies. Fault tolerance techniques can be used in order to improve the circuit's reliability but leading to some kind of design penalties (area, time, power consumption). In this work, we propose a method that takes into account reliability and other classic design parameters when choosing the most suitable architecture. In addition, the designer is free to establish different cost-performance tradeoffs according to the target application.
AB - Reliability is becoming an important feature of digital circuits implemented on deep submicron technologies. Fault tolerance techniques can be used in order to improve the circuit's reliability but leading to some kind of design penalties (area, time, power consumption). In this work, we propose a method that takes into account reliability and other classic design parameters when choosing the most suitable architecture. In addition, the designer is free to establish different cost-performance tradeoffs according to the target application.
U2 - 10.1109/MWSCAS.2010.5548767
DO - 10.1109/MWSCAS.2010.5548767
M3 - Conference contribution
AN - SCOPUS:77956567066
SN - 9781424477715
T3 - Midwest Symposium on Circuits and Systems
SP - 1250
EP - 1253
BT - 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010
T2 - 53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010
Y2 - 1 August 2010 through 4 August 2010
ER -