A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI

Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.