A SOPC oriented FPGA implementation of JPEG-2000 entropy coder

An overview is given of the implementation of the entropy coder on programmable circuits FPGA Xilinx Virtex-II. The implementation runs at 71 Mhz for about 220,000 equivalent system gates which place the circuit in the reach of a Virtex II XV250-6-CS144 chip or a 2VP250 Pro. This approach is more general and cost effective than existing proposed products for JPEG-2000 coders since the chip keeps full multiprocessing capabilities for other processing while still having its dedicated logic free to be dynamically reconfigured to serve for other computationally intensive processing.