A SPICE-like DC model for organic thin-film transistors

Omid Yaghmazadeh; Yvan Bonnassieux; Amar Saboundji; Bernard Geffroy; Denis Tondelier; Gilles Horowitz

doi:10.3938/jkps.54.523

A SPICE-like DC model for organic thin-film transistors

Omid Yaghmazadeh
, Yvan Bonnassieux
, Amar Saboundji
, Bernard Geffroy
, Denis Tondelier
, Gilles Horowitz

Institut polytechnique de Paris
Université Paris Diderot

Résultats de recherche: Contribution à un journal › Article › Revue par des pairs

18 Citations (Scopus)

Résumé

We have developed a SPICE-like DC model for pentacene thin film transistors by using Verilog-A language. This model is based on an adapted MOSFET model for amorphous silicon TFTs (AIM-SPICE Level 15). A complete parameter extraction procedure has also been established and validated.

langue originale	Anglais
Pages (de - à)	523-526
Nombre de pages	4
journal	Journal of the Korean Physical Society
Volume	54
Numéro de publication	1 PART 2
Les DOIs	https://doi.org/10.3938/jkps.54.523
état	Publié - 1 janv. 2009

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10.3938/jkps.54.523

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title = "A SPICE-like DC model for organic thin-film transistors",

abstract = "We have developed a SPICE-like DC model for pentacene thin film transistors by using Verilog-A language. This model is based on an adapted MOSFET model for amorphous silicon TFTs (AIM-SPICE Level 15). A complete parameter extraction procedure has also been established and validated.",

keywords = "Organic thin-film transistors, Otft modeling, Parameter extraction, Verilog-A",

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AU - Yaghmazadeh, Omid

AU - Bonnassieux, Yvan

AU - Saboundji, Amar

AU - Geffroy, Bernard

AU - Tondelier, Denis

AU - Horowitz, Gilles

PY - 2009/1/1

Y1 - 2009/1/1

N2 - We have developed a SPICE-like DC model for pentacene thin film transistors by using Verilog-A language. This model is based on an adapted MOSFET model for amorphous silicon TFTs (AIM-SPICE Level 15). A complete parameter extraction procedure has also been established and validated.

AB - We have developed a SPICE-like DC model for pentacene thin film transistors by using Verilog-A language. This model is based on an adapted MOSFET model for amorphous silicon TFTs (AIM-SPICE Level 15). A complete parameter extraction procedure has also been established and validated.

KW - Organic thin-film transistors

KW - Otft modeling

KW - Parameter extraction

KW - Verilog-A

U2 - 10.3938/jkps.54.523

DO - 10.3938/jkps.54.523

M3 - Article

AN - SCOPUS:60049090772

SN - 0374-4884

VL - 54

SP - 523

EP - 526

JO - Journal of the Korean Physical Society

JF - Journal of the Korean Physical Society

IS - 1 PART 2

ER -

A SPICE-like DC model for organic thin-film transistors

Résumé

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