@inproceedings{0743f038d03a4d89821f3b888ec5db14,
title = "A technique to reduce the impact of hysterisys in ΔΣ analog to digital converters",
abstract = "This paper deals with dynamic latch hysterisys and its effects on ΔΣ modulators. It sheds light on the difference between its impact on low pass and high pass modulators. It also presents a technique to reduce its effect on low pass ΔΣ modulators. This technique was tested using a 2nd order feed forward ΔΣ modulator. The employed dynamic latch was designed in a 1.2 V 65 nm CMOS technology. It has an hysterisys of 27 mv at 220 MHz. A Signal to Noise Ratio improvement of 9 dB was achieved using the proposed technique compared to the classical implementation.",
keywords = "Dynamic latch, Hysterisys, Sigma-delta",
author = "Chadi Jabbour and Nguyen, \{Van Tam\} and Patrick Loumeau",
year = "2010",
month = aug,
day = "31",
doi = "10.1109/ISCAS.2010.5537640",
language = "English",
isbn = "9781424453085",
series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",
pages = "4017--4020",
booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",
note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",
}