TY - GEN
T1 - ALTIROC1, a 25 ps Time Resolution ASIC for the ATLAS High Granularity Timing Detector
AU - Agapopoulou, C.
AU - Dinaucourt, P.
AU - Dragone, A.
AU - Gong, D.
AU - de la Taille, C.
AU - Makovec, N.
AU - Markovic, B.
AU - Martin-Chassard, G.
AU - Milke, C.
AU - Morenas, M.
AU - Ruckman, L.
AU - Sacerdoti, S.
AU - Schwartzman, A.
AU - Seguin-Moreau, N.
AU - Serin, L.
AU - Su, D.
AU - Ye, J.
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020/1/1
Y1 - 2020/1/1
N2 - 1 Abstract-Designed and characterized by the HGTD collaboration, ALTIROC belongs to the family of readout ASICs used at the Large Hadron Collider (LHC) for the High Luminosity-LHC upgrade. ALTIROC1 is a 25-channel ASIC designed in CMOS 130 nm to read out the 5 x 5 matrix of 1.3 mm x 1.3 mm Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and its readout electronics from 35 ps/hit (initial) to 70 ps/hit (end of operational lifetime). Each ASIC channel integrates an RF preamplifier followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold measurements as well as a local memory. This front-end must exhibit an extremely low jitter noise while keeping a challenging power consumption of less than 4.5 mW per channel. This conference proceeding summarizes the ASIC's architecture, its measured performances compared to simulation, along with the requirements for the HEP experiments.
AB - 1 Abstract-Designed and characterized by the HGTD collaboration, ALTIROC belongs to the family of readout ASICs used at the Large Hadron Collider (LHC) for the High Luminosity-LHC upgrade. ALTIROC1 is a 25-channel ASIC designed in CMOS 130 nm to read out the 5 x 5 matrix of 1.3 mm x 1.3 mm Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and its readout electronics from 35 ps/hit (initial) to 70 ps/hit (end of operational lifetime). Each ASIC channel integrates an RF preamplifier followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold measurements as well as a local memory. This front-end must exhibit an extremely low jitter noise while keeping a challenging power consumption of less than 4.5 mW per channel. This conference proceeding summarizes the ASIC's architecture, its measured performances compared to simulation, along with the requirements for the HEP experiments.
UR - https://www.scopus.com/pages/publications/85124687828
U2 - 10.1109/NSS/MIC42677.2020.9507972
DO - 10.1109/NSS/MIC42677.2020.9507972
M3 - Conference contribution
AN - SCOPUS:85124687828
T3 - 2020 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2020
BT - 2020 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2020
Y2 - 31 October 2020 through 7 November 2020
ER -