An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

Josep Torras Flaquer; Jean Marc Daveau; Lirida Naviner; Philippe Roche

doi:10.1109/IOLTS.2011.5993818

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

Josep Torras Flaquer
, Jean Marc Daveau
, Lirida Naviner
, Philippe Roche

STMicroelectronics SA, France
Telecom Paris

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

5 Citations (Scopus)

Résumé

We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

langue originale	Anglais
titre	Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
Pages	98-103
Nombre de pages	6
Les DOIs	https://doi.org/10.1109/IOLTS.2011.5993818
état	Publié - 19 sept. 2011
Evénement	2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 - Athens, Grcce Durée: 13 juil. 2011 → 15 juil. 2011

Série de publications

Nom	Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

Une conférence

Une conférence	2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
Pays/Territoire	Grcce
La ville	Athens
période	13/07/11 → 15/07/11

Accès au document

10.1109/IOLTS.2011.5993818

Contient cette citation

Flaquer, J. T., Daveau, J. M., Naviner, L., & Roche, P. (2011). An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. Dans Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 (p. 98-103). Article 5993818 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011). https://doi.org/10.1109/IOLTS.2011.5993818

Flaquer, Josep Torras ; Daveau, Jean Marc ; Naviner, Lirida et al. / An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 98-103 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

@inproceedings{b2a5c687a86341159aae3aca0e7afbfa,

title = "An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities",

abstract = "We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.",

keywords = "SER, SET, circuit clustering, circuit reliability, logic design, probability, reliability estimation",

author = "Flaquer, \{Josep Torras\} and Daveau, \{Jean Marc\} and Lirida Naviner and Philippe Roche",

year = "2011",

month = sep,

day = "19",

doi = "10.1109/IOLTS.2011.5993818",

language = "English",

isbn = "9781457710551",

series = "Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011",

pages = "98--103",

booktitle = "Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011",

note = "2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 ; Conference date: 13-07-2011 Through 15-07-2011",

}

Flaquer, JT, Daveau, JM, Naviner, L & Roche, P 2011, An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. Dans Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011., 5993818, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, p. 98-103, 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, Athens, Grcce, 13/07/11. https://doi.org/10.1109/IOLTS.2011.5993818

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. / Flaquer, Josep Torras; Daveau, Jean Marc; Naviner, Lirida et al.
Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 98-103 5993818 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

TY - GEN

T1 - An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

AU - Flaquer, Josep Torras

AU - Daveau, Jean Marc

AU - Naviner, Lirida

AU - Roche, Philippe

PY - 2011/9/19

Y1 - 2011/9/19

N2 - We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

AB - We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

KW - SER

KW - SET

KW - circuit clustering

KW - circuit reliability

KW - logic design

KW - probability

KW - reliability estimation

U2 - 10.1109/IOLTS.2011.5993818

DO - 10.1109/IOLTS.2011.5993818

M3 - Conference contribution

AN - SCOPUS:80052696786

SN - 9781457710551

T3 - Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

SP - 98

EP - 103

BT - Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

T2 - 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

Y2 - 13 July 2011 through 15 July 2011

ER -

Flaquer JT, Daveau JM, Naviner L, Roche P. An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. Dans Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 98-103. 5993818. (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011). doi: 10.1109/IOLTS.2011.5993818

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

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Série de publications

Une conférence

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