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An efficient modeling and execution framework for complex systems development

  • Isabelle Perseil
  • , Laurent Pautet
  • , Jean François Rolland
  • , Mamoun Filali
  • , Didier Delanote
  • , Stefan Van Baelen
  • , Wouter Joosen
  • , Yolande Berbers
  • , Fréderic Mallet
  • , Dominique Bertrand
  • , Sébastien Faucou
  • , Abdelhafid Zitouni
  • , Mahmoud Boufaida
  • , Lionel Seinturier
  • , Joel Champeau
  • , Thomas Abdoul
  • , Peter H. Feiler
  • , Chokri Mraidha
  • , Sébastien Gérard
  • CNRS LTCI
  • Universite Paul Sabatier
  • KU Leuven
  • Université Côte D’Azur
  • Université de Nantes
  • Univ. Mentouri de Constantine
  • Université de Lille
  • ENSTA Bretagne
  • Carnegie Mellon University
  • LIST-DTSI-SLA CEA

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collectionContribution à une conférenceRevue par des pairs

5 Citations (Scopus)

Résumé

In this paper, we present different modeling and execution frameworks that allow us to efficiently analyze, design and verify complex systems, mainly to cope with the specific concerns of the Real-time and embedded systems (RTE) domain. First we depict a UML1/MARTE2 based methodology for executable RTE systems modeling with a framework and its underlying model transformations required to execute UML models conforming to the MARTE standard. The advantages of adopting a more generic action language with formal features are highlighted, in order to raise the level of abstraction with formal features. Then, we investigate how MARTE, with its Time Model facilities, can be made to represent faithfully AADL3 periodic/aperiodic tasks communicating through event or data ports, in an approach to end-to-end flow latency analysis. An analytical framework allows us to optimize port-based communication by generating a runtime executive that utilizes shared data areas where appropriate, while ensuring the timing semantic assumed by the control application. An analysis of the AADL mode change protocol is also provided, exposing a translation process that takes as an input an AADL model and produces as an output a time Petri net. We show how an AADL model transformation provides a formal model for model checking activities and we suggest that model transformation provides useful support to improve the integration of formal verification in an industrial engineering process. As a case study we use an implementation of a UDP4/IP5 protocol stack.

langue originaleAnglais
titreProceedings - 2011 16th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2011
EditeurIEEE Computer Society
Pages317-331
Nombre de pages15
ISBN (imprimé)9780769543819
Les DOIs
étatPublié - 1 janv. 2011
Modification externeOui

Série de publications

NomProceedings - 2011 16th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2011

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