Assessing Security RISC: Analyzing Flush+Fault Attack on RISC-V Using gem5 Simulator

Microarchitectural side-channel attacks exploit vulnerabilities such as cache behavior to leak sensitive data. These attacks have been extensively studied on x86 architectures but they remain less explored on RISC-V systems. A recent paper (Gerlach et al., 2023) demonstrated existing and novel microarchitectural attacks on RISC-V hardware platforms (C906, U74, C910, C908). This hardware-based analysis, while realistic, lacks the flexibility and detailed behavioral insights needed to fully understand these attacks. Simulation environments like gem5 (Lowe-Power, 2024) provide fine-grained control and diverse metrics to overcome this limitation and observe the attack in detail. In this paper, gem5 is used to explore Flush+Fault (Gerlach et al., 2023) side-channel attack on RISC-V architecture which was originally tested on RISC-V hardware. Through gem5, we analyze detailed insights of attack such as cache patterns, and timing behaviors. Our results demonstrate the gem5’s potential for advancing the understanding of RISC-V microarchitectural vulnerabilities and eventually for developing effective countermeasures.