Assisting abstraction and verification of IP modules by control-data slicing

Functional verification of hardware modules is growing to be challenging due to strict timing requirements, power limitation and time-to-market pressure in design process. Removal of irrelevant information by abstraction of hardware computations has been used by the experts to speed up the verification process. We introduce a register transfer level (RTL) control-data slicing approach in intellectual property (IP) modules to assist formal verification and simulation based validation approaches by removing irrelevant information and reduce state space for model checking and save cycles for simulations. In this paper a control-data separation solution is presented based on slicing of RTL models. Slicing is helpful to identify and separate control state machine from data processing of the IP module to be used for static verification of the critical timing behaviors of the module. The data processing separated from critical control state machine is abstracted to improve verification by simulation without loss of timing information.