Asymmetrical length biasing for energy efficient digital circuits

Francisco Veirano; Fernando Silveira; Lirida Naviner

doi:10.1109/LASCAS.2017.7948060

Asymmetrical length biasing for energy efficient digital circuits

Francisco Veirano
, Fernando Silveira
, Lirida Naviner

Instituto de Ingeniería Eléctrica
Universidad de la República
Université Paris-Saclay

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

1 Citation (Scopus)

Résumé

In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.

langue originale	Anglais
titre	LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
Sous-titre	Proceedings
Editeur	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronique)	9781509058594
Les DOIs	https://doi.org/10.1109/LASCAS.2017.7948060
état	Publié - 13 juin 2017
Modification externe	Oui
Evénement	8th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2017 - Bariloche, Argentine Durée: 20 févr. 2017 → 23 févr. 2017

Série de publications

Nom	LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings

Une conférence

Une conférence	8th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2017
Pays/Territoire	Argentine
La ville	Bariloche
période	20/02/17 → 23/02/17

Accès au document

10.1109/LASCAS.2017.7948060

Contient cette citation

Veirano, F., Silveira, F., & Naviner, L. (2017). Asymmetrical length biasing for energy efficient digital circuits. Dans LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings Article 7948060 (LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS.2017.7948060

Veirano, Francisco ; Silveira, Fernando ; Naviner, Lirida. / Asymmetrical length biasing for energy efficient digital circuits. LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. (LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings).

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abstract = "In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50\% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.",

author = "Francisco Veirano and Fernando Silveira and Lirida Naviner",

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doi = "10.1109/LASCAS.2017.7948060",

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Veirano, F, Silveira, F & Naviner, L 2017, Asymmetrical length biasing for energy efficient digital circuits. Dans LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings., 7948060, LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings, Institute of Electrical and Electronics Engineers Inc., 8th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2017, Bariloche, Argentine, 20/02/17. https://doi.org/10.1109/LASCAS.2017.7948060

Asymmetrical length biasing for energy efficient digital circuits. / Veirano, Francisco; Silveira, Fernando; Naviner, Lirida.
LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 7948060 (LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

TY - GEN

T1 - Asymmetrical length biasing for energy efficient digital circuits

AU - Veirano, Francisco

AU - Silveira, Fernando

AU - Naviner, Lirida

PY - 2017/6/13

Y1 - 2017/6/13

N2 - In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.

AB - In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.

U2 - 10.1109/LASCAS.2017.7948060

DO - 10.1109/LASCAS.2017.7948060

M3 - Conference contribution

AN - SCOPUS:85022215494

T3 - LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings

BT - LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 8th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2017

Y2 - 20 February 2017 through 23 February 2017

ER -

Veirano F, Silveira F, Naviner L. Asymmetrical length biasing for energy efficient digital circuits. Dans LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 7948060. (LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings). doi: 10.1109/LASCAS.2017.7948060

Asymmetrical length biasing for energy efficient digital circuits

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