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Convolution blocks based on self-checking operators

  • Telecom Paris
  • Communications and Electronics Department

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Résumé

The arrival of CMOS integrated systems into nanoscale dimensions is presenting many challenges to designers and manufacturers concerning yield and reliability of integrated circuits. Traditional techniques to cope with these subjects are not as effective as they were before and many solutions are considered to allow CMOS evolution to continue according to Moore's law. Among the proposed solutions in the literature there's self-checking design and circuit reconfiguration. In the present work we introduce self-checking arithmetic operators in the design of convolution processors and we verify the penalties of such solutions in terms of area and speed. The self-checking methods considered are parity prediction, duplication and 1-out-of-3 encoding.

langue originaleAnglais
titreProceedings of the 14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007
Pages487-491
Nombre de pages5
Les DOIs
étatPublié - 1 déc. 2007
Evénement14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007 - Ciechocinek, Pologne
Durée: 21 juin 200723 juin 2007

Série de publications

NomProceedings of the 14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007

Une conférence

Une conférence14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007
Pays/TerritoirePologne
La villeCiechocinek
période21/06/0723/06/07

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